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Assessment Cover Sheet and Feedback Form 2023-24

Module Code: E.g. CS3S666	Module Title:		Module Team:Name
Assessment Title and Tasks:  _Practical Assessment 1			Assessment No.  1
Date Set: dd-mmm-yyyy.		Submission Date:  dd-mmm-yyyy.	Return Date: dd-mmm-yyyy.

IT IS YOUR RESPONSIBILITY TO KEEP RECORDS OF ALL WORK SUBMITTED

Marking and Assessment

This assignment will be marked out of 100% This assignment contributes to 50% of the total module marks.

Learning Outcomes to be assessed (as specified in the validated module descriptor):  1) Able to demonstrate knowledge and understanding of the equipment, materials and processes and test strategies employed within an electronic manufacturing environment.2) Will be able to understanding the principles of managing engineering processes, to include new product introduction and concurrent engineering.

Marking Criteria/Marking Scheme See Following Page for Marking Guide

Provisional mark only: subject to change and / or confirmation by the Assessment Board

Marking	Max	Grade	Marks	Rationale
Q1	15	70 -100 (1st)		A perfectly created schematic, using appropriate components, with all necessary parts for DFT and DFM. The different sections of the schematic are clearly identified
		60 – 69 (2:1)		A well-thought-out schematic, but with some minor faults.
		50 – 59 (2:2)		A schematic that is readable and contains some good parts, but with some flaws. The simulation is fully running but with some flaws in the results.
		40 – 49 (3rd)		A poorly organised schematic, where some of the functionalities are not present or that the simulation is not fully running.
		0-39 (Fail)		An incomplete schematic, where the functionalities are not all present, and that simulation is not properly running.
Q2	15	70 -100 (1st)		The simulation is fully functional and demonstrates that all the requirements are met
		60 – 69 (2:1)		The simulation is partially functional and demonstrates that some of the requirements are met
		50 – 59 (2:2)		A simulation is partially functional and contains some good parts, but with some flaws in the results.
		40 – 49 (3rd)		A poorly organised simulation, where some of the functionalities are not present or running.
		0-39 (Fail)		An incomplete simulation, where the functionalities are not all present or incorrect.
Q3	20	70 -100 (1st)		A perfectly created layout, using appropriate footprints, with all necessary parts for DFT and DFM. Perfect silk position and references. All layers appropriately used and labelled.
		60 – 69 (2:1)		A very good layout, using appropriate footprints, with all necessary parts for DFT and DFM. Good silk position and references. Layers mostly appropriately used and labelled.
		50 – 59 (2:2)		Overall good layout, using appropriate footprints, with all necessary parts for DFT and DFM. Good silk position and references. Layers mostly appropriately used and labelled.
		40 – 49 (3rd)		Functional layout with most of the appropriate parts for DFM and DFT. Most of the silk there but with room for improvement.
		0-39 (Fail)		Poorly executed layout, some missing parts or incorrect footprint.
Q4	30	70 -100 (1st)		A perfect presentation, following a logical structure and with referencing done correctly. And a complete BOM.
		60 – 69 (2:1)		A well-thought-out presentation, but with some minor faults. And a complete BOM with minor flaws.
		50 – 59 (2:2)		A presentation that is readable and contains some referencing, but not in a logical fashion.  And near complete BOM with minor flaws.
		40 – 49 (3rd)		A poorly organised presentation, where information is not organised in a logical manner or without referencing. And a partial but mostly correct BOM
		0-39 (Fail)		An unorganised presentation, where information does not follow a logical procedure. Missing or incorrect BOM.
Q5	20	70 -100 (1st)		A well thought out test plan with sensible thresholds
		60 – 69 (2:1)		The work was complete and in the correct format. The work undertaken was described accurately in a good logical format.
		50 – 59 (2:2)		Although complete test plan and thresholds, they lacked clarity in some areas.
		40 – 49 (3rd)		Attempt at devising a test plan and threshold but with some errors.
		0-39 (Fail)		A poor thought out test plan.
Total Mark:

Sweeping LED

Product specification

A customer has given us a specification for an electronic product to be designed:

• The product should have 10 LEDs lighting up in a sweeping pattern (as follow)
  
• The LEDs should be orange 
• Each LED should be ON for 50ms
• The product should only be hardware based – no firmware
• The product is to be powered from a 24V AC source (from a 2 leads cable to a connector)
• The product is planned to be mass manufactured (10s of thousands) 
• The LEDs should be on the top side of the PCB, the remaining parts should be on the bottom side. 
• The LEDs should be set 5mm apart (from LED centre) 
• All components should be SMT

Features or requirements that have not been clearly established in the specification are relayed to the expertise of the design engineer. 

Tasks

1. Create a schematic, against above specification, on Proteus.

(15 Marks)

2. Simulate your schematic to check that it meets the specification. 

(15 Marks)

3. Create a PCB layout considering the requirements from the specification.

(20 Marks)

4. Write a report about your design process and decisions. Remember to take care of DFT (Design For Testability) and DFM (Design For Manufacturing) while designing the product, and generate a full BOM (Bill of Materials)

(30 Marks)

5. Report on the test method and process including pass/fail thresholds. 

 (20 Marks)