Advanced Manufacturing Systems: Full Wave Bridge Rectifier Design, EMI Filtering, PCB Development, And Lean Manufacturing Analysis

PUBLIC / CYHOEDDUSFaculty Of Computing and Engineering SciencesAssessment Cover Sheet and Feedback Form 2024-25

Module Code: NG3S909Module Title:Advanced Manufacturing SystemsModule Team:Alex Oleon, Hammad NazirAssessment Title and Tasks:_Practical Assessment 1Assessment No.1Date Set:02-Oct-23Submission Date:09-Dec-24Return Date:09-Jan-24

IT IS YOUR RESPONSIBILITY TO KEEP RECORDS OF ALL WORK SUBMITTED
Marking and AssessmentThis assignment will be marked out of 100%This assignment consists of two parts. Each part contributes to 50% of the total module marks.Plagiarism will be checked using Turnitin. Any kind of copy will be taken seriously resulting in academic misconduct.Learning Outcomes to be assessed (as specified in the validated module descriptor https://icis.southwales.ac.uk/ ):
Able to demonstrate knowledge and understanding of the equipment, materials and processes and test strategies employed within an electronic manufacturing environment.Will be able to understanding the principles of managing engineering processes, to include new product introduction and concurrent engineering.
Marking Criteria/Marking SchemeSee Following Page for Marking GuideProvisional mark only: subject to change and / or confirmation by the Assessment Board
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MarkingMaxGradeMarksRationaleQ11570 -100(1st)
A perfectly created schematic, using appropriate components, with all necessary parts for bridge rectifier. The different sections of the schematic are clearly identified60 – 69(2:1)
A well-thought-out schematic, but with some minor faults.50 – 59(2:2)
A schematic that is readable and contains some good parts, but with some flaws. The simulation is fully running but with some flaws in the results.40 – 49(3rd)
A poorly organised schematic, where some of the functionalities are not present or that the simulation is not fully running.0-39(Fail)
An incomplete schematic, where the functionalities are not all present, and that simulation is not properly running.Q21570 -100(1st)
The simulation is fully functional and demonstrates that all the requirements are met60 – 69(2:1)
The simulation is partially functional and demonstrates that some of the requirements are met50 – 59(2:2)
A simulation is partially functional and contains some good parts, but with some flaws in the results.40 – 49(3rd)
A poorly organised simulation, where some of the functionalities are not present or running.0-39(Fail)
An incomplete simulation, where the functionalities are not all present or incorrect.Q32070 -100(1st)
A perfectly created layout, using appropriate footprints. Perfect silk position and references. All layers appropriately used and labelled.60 – 69(2:1)
A very good layout, using appropriate footprints. Good silk position and references. Layers mostly appropriately used and labelled.50 – 59(2:2)
Overall good layout, using appropriate footprints. Good silk position and references. Layers mostly appropriately used and labelled.40 – 49(3rd)
Functional layout. Most of the silk there but with room for improvement.0-39(Fail)
Poorly executed layout.Q41070 -100(1st)
Thoroughly worked and well developed chart with inclusion of mostrelevant process functions and potential failure effects, causes, and controls with RPN. Valid and most effective action results.60 – 69(2:1)
A well-developed chart with possible potential functions and potential failure effects, causes, and controls with RPN. Valid effective action results.50 – 59(2:2)
Chart showing potential failure effects, causes, and controls with RPN and effective action results.40 – 49(3rd)
Attempt to develop a chart with potential failure effects, causes, and controls with RPN and action results.0-39(Fail)
A poor work with process functions and not suitable failure effects, causes,and controls with no/ poor RPN and effective action results.Q51070 -100(1st)
Very concise, informative and clear explanation provided around the arrangements of handling product to be safe from ESD60 – 69(2:1)
A very good explanation provided around the arrangements of handling product to be safe from ESD50 – 59(2:2)
A good level of information around the arrangements of handling product to be safe from ESD40 – 49(3rd)
Satisfactory but incomplete and not highlighting relevant arrangements of handling product to be safe from ESD0-39(Fail)
Poor/ Incorrect/ No arguments, explanations and reasoning of relevant arrangements of handling product to be safe from ESDQ61070 -100(1st)
Comprehensive calculations with all the necessary steps for mean and rangecalculations with their respective fully labelled charts
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60 – 69(2:1)
Correct calculations with all steps well written with respective well labelled charts50 – 59(2:2)
Calculations with few missing steps with respective well labelled charts40 – 49(3rd)
Attempt to perform calculations with respective charts not labelled properly0-39(Fail)
A poor work with wrong/ no/ or incomplete chartsQ7 and 81070 -100(1st)
Comprehensive calculations with all the necessary steps well written60 – 69(2:1)
Correct calculations with all steps well written50 – 59(2:2)
Calculations with few missing steps40 – 49(3rd)
Attempt to perform calculations0-39(Fail)
A poor work with totally wrong calculationsQ91070 -100(1st)
Comprehensive and well-structured VSM capturing the entire value stream.60 – 69(2:1)
Well-developed VSM that covers most essential process functions50 – 59(2:2)
Reasonably well-developed VSM but might be lacking in completeness or clarity.40 – 49(3rd)
VSM is presented, but it may lack thoroughness in capturing key process functions.0-39(Fail)
The VSM is of poor quality, lacking in the identification of key process functions.
Full Wave Bridge Rectifier Circuit with various EMI filters (110 Marks)Full Wave Bridge Rectifier converts AC to DC. EMI in AC-DC conversion begins with conducted currents into the input. Conducted EMI can also appear as common-mode or differential mode noise at various stages during power conversion. Different components are used at each stage in power conversion to reduce conducted EMI. EMI filters can be used to clean up the conducted EMI (noise) throughout a power conversion system. The full bridge rectifier with shunt capacitor filter is shown below.
Figure 1. The full bridge rectifier.PUBLIC / CYHOEDDUSTasks
You are required to create a schematic of a full bridge rectifier on Proteus against above figure and specifications and analyse the output signals without and with EMI filters. The EMI filters which you will use are CL, LC, π and T filters. You will place each filter at the output of bridge and analyse the results.
ComponentValue / Part ReferenceR10 kΩ, MINRES10KL68 uH, ELJ-SA680KBC2200 µF, HITEMP2200U25V1090MAlternator325V,50HzDiode1N4007TransformerTRAN-2P3SPrimary inductance: 180Connectors±12V, 0V, O/P and GND, CONN-SIL1
Figure 2. The EMI filters: CL, LC, π and T filters.(15 Marks)
Simulate your schematic and compare the results of all the rectifier type and find which filter type is best and why?
(15 Marks)
Create PCB layouts for each rectifier type considering the requirements from the following specification.
Keep the trace routing as short and as direct as possible. The shorter the routing, the less potential there is of generating EMI.Keep the traces for routing as wide as possible too. The wider the trace, the lower the inductance, which will also help to minimize EMI.Route high-current lines at 45 degrees instead of at right angles. Could you investigate and draft why 45 degree is better than 90 degree?Develop a 3D of your PCB using 3D visualizer.
Bonus marks question:
In your initial design without any filters, replace the THD rectifier diodes with Surface Mount Device (SMD) rectifier diodes in both the schematic capture and PCB layout. Identify the SMD counterpart for 1N4007.Mount SMT rectifier diodes on soldering side and other THD components on component side of pcb.
PUBLIC / CYHOEDDUS(4 x 5 = 20 Marks) Plus 10 bonus marks
Construct an FMEA for this product.
(20 Marks)
Discuss the necessary arrangements for handling this product so it stays safe from ESD.
(10 Marks)
In a PCB manufacturing industry the excessive heat test is performed to test high temperature capability. Excessive heat can lead to warping in the lengths, widths and thicknesses of different PCB layers and disruption of circuit lines. Excessive heat test is one of the important quality control factor. During testing phase, project team performed the PCB capability study. In Analyse phase collected 20 sets of PCB temperature samples with a subgroup size of 4.
Table – Temperature results from 20 PCB samplesCalculate the mean (X) and range value (R) for each subgroup and develop the X bar and R charts. From the calculation results and charts, do you think the process is controlled or out-of-control? Ensure the charts are clearly labelled.(10 Marks)
In a small PCB manufacturing plant, the total time available is 500 mins. per day and the total quantity of PCBs manufactured, as per costumers demand are 800 units. The total operator cycle time (Step #1 to Step #4) is shown in Table below. How many operators are required to meet the costumers demand?
Step #1Step #2Step #3Step #4Operator CycleTime = 5Operator CycleTime = 4Operator CycleTime = 4Operator CycleTime = 7
PUBLIC / CYHOEDDUSTable – Operator cycle time for each step of manufacturing(5 Marks)
For the Lean assembly, total operation time is 16 mins, and the customer demand for that period is 24 units. We can see that we have an estimated average inventory level of 12 units before the operation and average inventory level of 10 units after the cycle time (C/T). The cycle time is 8s as shown in figure:
Figure 3 – The waiting time and process time
Calculate Takt time?Calculate the waiting times before and after the 8s cycle time, shown by ‘?’ in figure?
(5 Marks)
Value Stream Mapping for Power Supply Manufacturing
Instructions: In this question, you are tasked with creating a value stream map (VSM) for a power supply manufacturing process. Value stream mapping is a vital tool in Lean and Six Sigma methodologies, helping organizations identify and eliminate waste in their processes. This exercise will give you an opportunity to apply VSM concepts and techniques to a real-world scenario.Scenario: You work for a company that produces power supplies used in various electronic devices. Your task is to map the current state of the manufacturing process for a specific power supply model, known as “PSX-2000.”Objective: Your goal is to create a value stream map that illustrates the entire process from raw materials to finished goods for the PSX-2000 power supply. This should help identify areas of improvement and inefficiency within the manufacturing process.Data and Cycle Time Information (for a single unit of PSX-2000):
Customer Demand: The customer demand for PSX-2000 is 100 units per day.Cycle Time: The cycle time for each process step is as follows:
Raw Material Inventory: 2 hoursComponent Assembly: 1.5 hoursQuality Control and Testing: 0.5 hoursFinal Assembly: 1 hourPackaging: 0.5 hours
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Shipping: 0.25 hours
Assigned Tasks:
Create a detailed value stream map for the manufacturing process of the PSX- 2000. Use the following symbols for your VSM:
Process BoxInventory TriangleTransportation ArrowPush ArrowKanbanData Box
Calculate and document the following key metrics for the current state of the process:
Lead Time (from raw materials to finished product)Cycle TimeProcess Time (time spent on value-added activities)Number of Process StepsInventory Levels (WIP)Total Processing TimeFirst Pass Yield (Quality)Downtime (if any)
Identify and label areas of waste within the value stream map. Use the 8 Wastes (TIMWOOD) framework to categorize waste and provide a brief description of each waste you identify.Based on your analysis, propose a future state value stream map that optimizes the manufacturing process, reducing waste and improving efficiency. Highlight the changes made and the expected impact on key metrics.
(10 Marks)~ End of Assignment ~